Study · Total no. of registers available for programmer:14

of Architecture and Programming model of 8086 Microprocessor


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8086 Microprocessor is an enhanced version of 8085
Microprocessor that was designed by Intel. It consists of powerful instruction
set, which provides operations like multiplication and division easily.

of 8086:

Data bus: 16 bit

Address bus 20 bit: 1 Mbytes (
1048576 bytes exactly)

Total no. of registers available for

Addressing modes: 2

supports two modes of operation, i.e. Maximum mode and Minimum mode.

mode works with system having multiple processors.

mode works with system having a single processor.

It can operate in single or multi
processor mode.

The architecture of 8086 supports a
16-bit ALU, a set of 16 – bit registers and provides segmented memory
addressing capacity, a rich instruction set, powerful interrupt structure,
pre-fetched instruction queue for overlapped fetching and execution.

Architecture of 8086

This is the diagram of the architecture of 8086












The complete architecture 8086 can
be divided into two parts:
1. Bus Interface Unit (BIU)

2. Execution Unit (EU)


Interface Unit:


It performs physical address
calculations and contains an instruction byte queue (6 bytes). This unit is
responsible for establishing communications with external devices and
peripherals including memory via the address and data bus.

BIU contains the following different

Segment Registers

Instruction Byte Queue

Address Conversion mechanism

Instruction Pointer(IP)


Segment Registers

The complete 1MB memory, which the
8086 is able to address, is divided into 16 logical segments. Each segment thus
contains 64kb locations. There are 4 segment registers:

Code Segment Register(CS)

The code segment register (CS) is used for addressing a
memory location in the code segment of the memory where executable program is

Data Segment Register(DS)

The data segment register points to the data segment of
memory where the data (I/P / O/P) is stored.

Extra Segment Registers

extra segment register (ES) refers to the segment which essentially is another
data segment of memory, thus extra segment also contains data.

Stack Segment Register

The stack segment register (SS) is used for addressing stack
segment of memory which is used to store stack data. The CPU uses stack
for temporarily storing data. Such as return addresses, contents of registers
before calling a subroutine.


Instruction Byte Queue

The 8086 has 6 byte instruction


It has first in first out data
structure. The instruction from queue is taken for decoding sequentially. Once
a byte is decoded the queue is rearranged by pushing it out and queue status is
checked for the possibility of next op code fetch cycle.


Address Conversion Mechanism

segment register indicates the base address of a particular segment .Since the
offset is a 16 bit no., each segment can have a maximum of 64K locations.
The BIU has an adder to perform this procedure for obtaining a physical address
while addressing memory. It adds the segment address
register depending upon whether the code, data or stack are
to be accessed while the offset may be the contents of IP,BX,SI,DI,SP
or an immediate 16 bit value, depending upon the addressing mode.
It generates 20 bit address by shifting segment register 4 bits left
&inserting 4 zero bits & and adds to it corresponding offset register




The EU contains the following parts:

General Purpose

There are a total of 8
general purpose registers. These are AL, AH, BL, BH, CL, CH, DL, DH.
Individually, these registers can hold up to 8-bit data and as a pair they can hold
up to 16-bits of information. These pairs are referred as AX, BX, CX, DX.

AX: –

This register is also known as Accumulator. It stores operands for
arithmetic operations.

BX: –

This is known as the base register. It stores the starting base
address of the memory area within the data segment.

CX: –

This is known as the counter. It stores the loop counter used in
the loop instruction.

DX: –

This register holds the I/O port address needed for I/O


Pointers and Index registers

The EU contains pointers except IP. The BP (Base Pointer)
and SP (Stack Pointer) usually contains offsets within the (code, data) and
(stack) segment respectively. The index registers are used as general purpose
registers as well as for offset storage in case of indexed, based indexed and
relative base indexed addressing modes. The register SI is generally used to
store the offset of source data in data segment while register DI is used to
store offset of destination in data or extra segment. The index registers are
particular for string manipulations.

Arithmetic and Logic Unit(ALU)

8086 has 16 bit ALU which is able to perform arithmetic and
logic operations. The 16 bit flag register reflects the result of execution by

Flag register

8086 has 16 bit flag register which is divided into 2 parts:
 Condition or Status flags. The condition code flag register is lower
byte of 16 bit flag register along with overflow flag, which is not present in 8085.
This part of flag register of 8086 reflects the results of ALU. The control
flag register is higher byte of flag register of 8086 affect operation of ALU.
The control flag register is higher byte of flag. The different types of flags

Conditional Flags