As environment which meets various requirements of SoC verification

As the size and complexity of SoC design grow, an efficient
and structured verification environment is becoming more important than ever
before. It is because many engineers with different knowledge and skills are
involved in SoC verification, and they have to deal with different aspects of
verification. This paper looks over the diversity of SoC verification and
suggests a practical application method of Efficent Verification methodology to
build an efficient and structured verification environment which meets various
requirements of SoC verification and IP’s Verification. This paper shows
standardized and well-organized testbench architecture that includes directory
structure of testbench files, and mechanism such as interface and handles
across the components. The proposed Efficent Verification methodology
application method helps testbench developers maintain consistency of
testbenches and reduce the quality gap among verification works that are done
by multiple verification engineers, by using standardized testbench. It ensures
that IP verification engineers do their job independently and the testbenches
can be reused in top level verification environment. In addition, it provides a
good infrastructure to hardware designers, who have little knowledge about
verification languages and methodologies, and who want to write directed test
cases only. The proposed method has been validated with a set of reference
testbenches developed for a Communication based SoC and Various IP’s.



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This verification methodology
is allowing of reusable verification components, flexible
and assembling immense test environments utilizing functional coverage
methodologies and constrained random stimulus generation. Its main promise is
to progress testbench reuse for Various IP’s and SOC. In this methodology
call-backs were updated and some call-back objections are added. Using these
improvements construct a reusable and efficient testbench for verification of
various IP’s and SoC. Testbench includes Environment, package, test and top
level Virtual sequencer and sequence blocks. Changes made in the constraints of
sequence, driver and scoreboard logic remaining code will be same for the every
IP/SoC. Using efficient methodology can acheve less time consuming.
Verification reusbiity increased i.e can use single test bench for various IP,s
and SoC.


Reusable Verification Environment

2. Transaction-Level Modeling (TLM)

 This methodology uses TLM standard to describe communication
between verification components in a verification environment. Because
efficient methodology standardizes the way components are connected, components
are interchangeable as long as they provide and require the same interfaces.
One of the main advantages of using TLM is in abstracting the pin and timing
details. A transaction, the unit of information exchange between TLM
components, encapsulates the abstract view of stimulus that can be expanded by
a lower-level component. One the pitfalls that can undermine the value of TLM
is adding excessive timing details by generating transaction and delivering
them on each clock cycle.

4. Configurability

Configurability, an enabler to productivity
and reuse, is a key element in this VM. In this, user can change the behavior
of an already instantiated component by three means: configuration API, Factory
overrides and callbacks.

6. Emphasis on reuse (vertical and horizontal)

All the tenets mentioned above lead to another
important goal which is reuse. Extensibility, configurability and layering
facilitate reuse. Horizontal reuse refers to reusing Verification IPs (VIPs)
across projects and vertical reuse describes the ability to use block-level
VIPs in cluster and chip level verification environments.

Virtual Sequencer:

Virtual sequence:

Environment reuse:

Interface signals should always be driven
using nonblocking assignments. In UVM framework we use “clocking blocks ” in
the interface .An interface block uses a clocking block to specify the timing
of synchronous signals relative to the clocks.

Any signal in a clocking block is now driven or sampled
synchronously, ensuring that your testbench interacts with the signals at the
right time.

In the UVM driver class we are converting the class based
transactions from sequencer into Physical signals (pin wiggles) understood by
DUT.Also we will use the Virtual interface handle to drive the values to the
actual interface.

You should always drive interface signals in a clocking block
with a synchronous drive using the <= operator.This is because the design signal does not change immediately after your assignment – remember that your testbench executes in the Reactive region while design code is in the Active region. ·         To understand what do you mean by Reactive and Active region. ·         In UVM Monitor components you will use blocking assignments as you are observing the transactions that are sent to the DUT which are class based.Transaction based communication doesn't care about timing relationship between sender and receiver.   Various IP's and SoC verified using unique testbench: Ethernet: I2SBus: UART: AXI Interface: I2C : USB: Communication based SoC: